1. Field of the Invention
The present invention relates to a method and apparatus for detecting a data error which can reliably detect whether or not an error took place in a data stored in a memory of a computer system or the like.
2. Description of the Related Art
An example of computer systems is an on-line system which is shown in FIG. 4. In the drawing, the on-line system comprises a host computer 1 and a terminal unit 7 which are connected by a signal cable 6 to each other. More specifically, the signal cable 6 connects communication controllers 5 and 8 respectively included in the host computer 1 and the terminal unit 7. The host computer 1 includes a data base 3, a memory 4, the aforementioned communication controller 5, and a central processing unit (CPU) 2 which is connected to these constituent parts 3, 4 and 5 to control these parts. The terminal unit 7, on the other hand, includes the aforementioned communication controller 8, a ROM 10, a RAM 11 protected by a battery 12 (which battery may be omitted in some applications), a keyboard input unit 13, a display unit 14, and a central processing unit (CPU) 9 which is connected to these parts 8, 10, 11, 13 and 14 to control the parts.
Referring to FIG. 5, there is shown a storage region of a memory 100 which comprises the ROM 10 and the RAM 11 in the terminal unit 7. In the drawing, the storage region comprises an lPL program zone 103, a terminal program load zone 104, a terminal control program load zone 105, a working area 106 and a check sign area 107.
The operation of such a terminal unit 7 will be explained in accordance with a flowchart shown in FIG. 6. First, when the power supply is turned ON or the CPU 9 is reset, the terminal unit 7 is energized (step 201). This causes the program of the lPL program zone 103 to be initiated so that the CPU 9 starts its operation (step 202). And the CPU 9 generates a check sum sign for the data of the terminal program load zone 104 and compares it with the corresponding check sum sign already stored in the check area 107 to detect a coincidence or noncoincidence therebetween (step 204). The CPU 9, when detecting a coincidence at the step 204, causes a signal indicative of unnecesary loading of any program to be sent to the host computer 1 (step 205) and starts its terminal control (step 211). On the other hand, the CPU 9, when detecting a non-coincidence at the step 204, causes a signal indicative of necessary loading of a program to be sent to the host computer 1 [step 206), and starts its program loading processing. -And the CpU 9 receives through the communication controller 8 signals transmitted from the host computer 1 (step 207) until it receives an end signal and it continues to store the data into the program load zone 104 of the RAM 11 (steps 208 and 209). When detecting the end signal, the CPU 9 generates a check sum signal for the data stored in the program load zone 104, stores it into the check sign area 107 (step 210), and starts its terminal control operation (step 211).
Now explanation will be made as to how to generate the check sum sign by referring to FIG. 7. It is now assumed that one of the blocks have addresses from a to (b -1) and capable of storing data .omega..sub.a, .omega..sub.a+1, . . . , and .omega..sub.b-1, respectively. In this case, the check sum sign corresponds to the lowest one byte of a sum .omega. of .omega..sub.a, .omega..sub.a+1, . . . , and .omega..sub.b-1. Check sum signs are sequentially obtained and stored through such a procedure as mentioned above so that a new check sum sign obtained at a predetermined time through the above procedure can be compared with the corresponding check sum sign previously held for error check.
Such check sum sign, which can be easily generated in a short time, has been widely used to positively detect a one-bit error.
However, in the event where 2-bit error takes place as shown in FIG. 8, the check sum sign method cannot detect the 2-bit error any longer. More in Detail, this method is defective in that, in the case where a bit 2 at an address (a+i) changes from "1" to "0" and a bit 2 at an address (a+j) changes from "0" to "1"; .omega..sub.a, .omega..sub.a+1, . . . , .omega..sub.a+1 -2.sup.2, .omega..sub.a+j +2.sup.2, . . . , .omega..sub.-1 are added together in order to generate a check sum sign, but its sum becomes X that is exactly the same as the sum X at the normal time, thus making it impossible to detect the error.
As has been mentioned above, the prior art method for detecting an error in data stored in a memory has had such a problem that, since the prior art method is based on the aforementioned one-bit check sum sign alone, it cannot detect a 2-bit error though it can detect a one-bit error.
The present invention has been made to solve the above problem in the prior art data error detecting method, and an object of the invention is to provide a method and system for detecting a data error which can reliably detect a 2-bit error in addition to a one-bit error.